1. Field of the Invention
This invention relates to a method and a device for addressing a memory and more particularly to a method including the arithmetic modification of one part of a memory address in accordance with a value specified by a second part of the address.
2. Prior Art
Within memory access techniques there is a need to use address words of suitable size in order to have access to suitably sized memory data fields. Sometimes it is convenient to address just a small data field, other times a large one. According to "Electronic Digital Systems" by R. K. Richards, published in 1966 by John V. Lay et Sons, pages 135 and 136, it is known to use an address word, where a given part of the address specifies the quantity of memory data, to which access is made by the addressing.
The problem of this method of addressing is that the data quantity defining part of the address grows too large, if varying data fields are to be addressed. If, for instance, it is desirable to use address words of constant length, the active address part will be small in the address word, if the data defining part becomes large.
One embodiment of the above mentioned known addressing system is shown in U.S. Pat. No. 4,126,897, inventor: Capowski et al, wherein an address word of constant length marking bits are used in order to obtain access to single-, double-, square- or N-words.
In IBM Technical Disclosure Bulletin, Vol. 18, No. 7, December 1975 there is described on page 2234 an addressing system, where 24 as well as 32 bits address words are used, these addresses being distinguished by a marking bit. The disadvantage of using address words of varying length is the fact that the architectural construction of the system becomes considerably more complicated.